Processor Core Architecture

• 9-issue, superscalar, 32-bit micro architecture optimized for high-frequency operation
• 3 parallel x86 Instruction Decoders
• Dynamic scheduling with speculative out-of order execution
• 2048-entry Branch Prediction Table and 12-entry Return Stack
• 3 superscalar, out-of-order integer pipelines, each containing
  - Integer execution unit
  - Address generation unit
• 3 superscalar, out-of-order multimedia pipelines
• FADD, MMX® ALU, 3DNow!™ technology
  - FMUL, MMX ALU (includes Mul and MAC), 3DNow! technology
  - FSTORE
• Level 1 64K-bit System Interface
• Multilevel TLB (24/256-entry I, 40/256-Entry D)
• 2 general purpose 64-bit load/store ports into D-cache
• High-speed 64-bit System Interface

• Deep internal buffering to support pipelines and external interfaces
  - Up to 72 x86 instructions in-flight
  - 32 outstanding load misses
  - 18-entry integer scheduler
  - 36-entry floating point scheduler
• 22 million transistors
• 85mm² die

Cache Architecture

• Level 1
  - 128k
  - 64k instruction, 64k data
  - Each 2-way associative
• Level 2
  - 256k
  - 16-way set associative
  - 64-bit L2 bus width